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w w w w wm8722 stereo dac with integrated tone generator and line/variable level outputs wolfson microelectronics ltd w :: www.wolfsonmicro.com advanced information, june 2001, rev 2.1 copyright ? 2001 wolfson microelectronics ltd. description the wm8722 is a high performance stereo dac designed for audio applications such as digital tv and set top boxes. the wm8722 has two stereo analogue outputs, one at line level and one that includes a digitally controllable mute and attenuator function. an on-chip tone generator can be routed through the line or variable outputs. wm8722 supports data input word lengths from 16-24 bits and sampling rates up to 96khz. the wm8722 consists of a serial interface port, digital interpolation filter, multi-bit sigma delta modulator and stereo dac in a small 20-pin ssop package. the 3 or 2-wire serial mpu compatible control port provides access to all features including tone generation, on-chip mute, attenuation and phase reversal. the programmable data input port supports glueless interfaces to popular dsps, audio decoders and s/pdif and aes/ebu receivers. features ? performance ? 102db snr (?a? weighted @48khz) ? -95db thd ? 5v or 3v supply operation ? sampling frequency: 8khz ? 96khz ? 3-wire or 2-wire serial mpu compatible interface for ? input data word; 16/20/24-bit ? soft mute ? de-emphasis ? volume control ? on-chip tone generator (1hz ? 32khz, 0.1 ? 25.5s) ? stereo analogue inputs ? 20-pin ssop package applications ? digital tv ? digital broadcast receivers ? set top boxes block diagram din bckin lrcin scki tone generator md mc latch digital attenuator and filters multi bit ? ? ? ? tone dac multi bit sc dac digital attenuator and filters multi bit ? ? ? ? multi bit sc dac mxinr mxinl lineoutl varoutl +6 to -73db, 1db steps varoutr lineoutr 0 to -46.5db, 1.5db steps cap avdd agnd dgnd + busy tclk +12 to -34.5db, 1.5db steps + + + 0/-6db 0/-6db 0/-6db mono attenuation control 4 l mix switches (0-9) +12 to -34.5db, 1.5db steps dvdd 0/-6db r mix switches (0-9) wm8722 serial interface control interface
wm8722 advanced information w w w w ai rev 2.1 june 2001 2 pin configuration ordering information device temp. range package xwm8722eds -25 to +85 o c 20-pin ssop mxinl cap dvdd din lrcin scki bckin dgnd md tclk avdd lineoutl varoutl lineoutr 16 15 14 20 19 18 17 5 6 7 1 2 3 4 mxinr busy latch mc 13 12 11 8 9 10 agnd varoutr pin description pin name type description 1 tclk digital input tone generator master-clock input. 2 mc digital input serial control data clock input (spi mode) or 2-wire clock input (2-wire mode) 3 md digital i/o serial control data input (spi mode) or 2-wire data input (2-wire mode) 4 latch digital input latch enable (spi mode) or address select (2-wire mode). 5 busy digital i/o interface format input pin (0= spi; 1 = 2-wire) or busy flag output. 6 dgnd supply digital ground supply. 7 mxinr analogue input analogue mixer input (right channel). 8 lineoutr analogue output right channel mixer output (line level). 9 varoutr analogue output right channel mixer output (variable level). 10 agnd supply analogue ground supply. 11 avdd supply analogue positive supply. 12 varoutl analogue output left channel mixer output (variable level). 13 lineoutl analogue output left channel mixer output (line level). 14 mxinl analogue input analogue mixer input (left channel). 15 cap analogue output analogue internal reference. 16 dvdd supply digital positive supply. 17 din digital input serial audio data input. 18 lrcin digital input sample rate clock input. 19 bckin digital input audio data bit clock input. 20 scki digital input system clock input (256 or 384fs). note: digital input pins have schmitt trigger input buffers.
wm8722 advanced information w w w w ai rev 2.1 june 2001 3 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max digital supply voltage -0.3v +7v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a 0 c +70 c storage temperature before soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c package body temperature (soldering 10 seconds) +240 c package body temperature (soldering 2 minutes) +183 c recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd -10% 3.3 to 5 +10% v analogue supply range avdd -10% 3.3 to 5 +10% v ground agnd, dgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v analogue supply current avdd = 5v 25 ma digital supply current dvdd = 5v 5 ma analogue supply current avdd = 3.3v 23 ma digital supply current dvdd = 3.3v 3 ma analogue supply current avdd = 5v, pwd = 1 1.5 ma digital supply current dvdd = 5v, pwd = 1 0.8 ma
wm8722 advanced information w w w w ai rev 2.1 june 2001 4 electrical characteristics test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit dac circuit specifications snr (note 1 and 2) avdd, dvdd = 5v, fs = 48khz 92 102 db avdd, dvdd = 3.3v, fs = 48khz avdd, dvdd = 5v, fs = 96khz 100 db thd (note 2) 0db -95 -85 db dynamic range (note 2) -60db 102 db passband 0.25db 0.4535fs hz stopband -3db 0.491fs hz passband ripple 0.25 db stopband attenuation f > 0.55fs 40 db channel separation 105 db gain mismatch channel-to-channel 1 5 %fsr digital logic levels input low level v il 0.8 v input high level v ih 2.0 v output low level v ol i ol = 1ma avss + 0.3v v output high level v oh i oh = 1ma avdd - 0.3v v analogue output levels output level into 10kohm, full scale 0db, (5v supply) 1.0 vrms into 10kohm, full scale 0db, (3.3v supply) 0.66 vrms to midrail or ac coupled (5v supply) 1 kohms minimum resistance load to midrail or ac coupled (3.3v supply) 600 ohms maximum capacitance load 5v or 3.3v 100 pf output dc level avdd/2 v reference levels potential divider resistance avdd to cap and cap to agnd 45 kohms voltage at cap avdd/2 por por threshold 1.6 v analogue mixer specifications snr 102 db thd 1v rms output, into 10kohm, 50pf load -100 -95 db dynamic range 102 db channel separation 105 db output voltage into 10kohm 1.5 vrms output current source 3 ma output current sink 2 ma input voltage, mxinl/r ac coupled 2 vrms mxinl/r input resistance 0db 50 kohm mxinl/r input resistance (at 12db trim) 20 kohm
wm8722 advanced information w w w w ai rev 2.1 june 2001 5 test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit gain mismatch channel to channel +/-1% +/-5% % of fsr frequency bandwidth 0db gain 100 khz master volume max gain 5 6 7 db master volume min gain -73 db master volume step size (note 4) 1 db master volume gain code 80 ? 127 (mute) -100 db mixer trim max gain 12 db mixer trim min gain -34.5 db mixer trim step size 1.5 db mono gain -7 -6 -5 db tone generator sinad (note 3) 1hz to 1khz tones 62 db sinad 1khz to 2khz tones 64 db sinad 2khz to 4khz tones 66 db sinad 4khz to 32khz tones 70 db full scale output voltage; trims at 0db 2.5 v pk-pk tone frequency tclk frequency = 27mhz 1 32767 hz tone duration tclk frequency = 27mhz 0.1 25.5 secs gain adjust range -46.5 0 db gain adjust step size (note 4) 1.5 db notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter, and where noted an ?a? weighted filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. sinad is ratio of signal to sum of noise, harmonics and spurii, over a bandwidth from 1hz up to either 127x the tone frequency, or 20khz, whichever is the lower. (this is to allow for the lower frequency tones having images at 127x and 129x the tone frequency which will fall in the audio band for tones of frequency less than about 20khz/128). 4. guaranteed monotonic. terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 6. pass-band ripple - any variation of the frequency response in the pass-band region.
wm8722 advanced information w w w w ai rev 2.1 june 2001 6 bckin din lrcin t bch t bcl t bl t lb t bcy t ds t dh figure 1 audio data input timing test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin pulse cycle time t bcy 100 ns bckin pulse width high t bch 40 ns bckin pulse width low t bcl 40 ns bckin rising edge to lrcin edge t bl 20 ns lrcin rising edge to bckin rising edge t lb 20 ns din setup time t ds 20 ns din hold time t dh 20 ns scki t sckil t sckih t scky figure 2 system clock timing requirements test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information system clock pulse width high t sckih 10 ns system clock pulse width low t sckil 10 ns system clock cycle time t scky 27 ns
wm8722 advanced information w w w w ai rev 2.1 june 2001 7 latch mc md t mhh t mld t mcy t mch t mcl t mds t mdh lsb t mls t mll figure 3 program register input timing ? 3-wire mpu serial control mode test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information mc pulse cycle time t mcy 100 ns mc pulse width low t mcl 40 ns md pulse width high t mch 40 ns md set-up time t mds 20 ns mc hold time t mdh 20 ns latch pulse width low t mll 20 ns latch pulse width high t mhh 20 ns latch set-up time t mls 20 ns latch delay from mc t mld 20 ns
wm8722 advanced information w w w w ai rev 2.1 june 2001 8 md mc t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 4 program register input timing ? 2-wire mpu serial control mode test conditions avdd, dvdd = 5v, agnd, dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information mc frequency 0 400 khz mc low pulsewidth t 1 600 ns mc high pulsewidth t 2 1.3 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns md, mc rise time t 6 300 ns md, mc fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns
wm8722 advanced information w w w w ai rev 2.1 june 2001 9 device description wm8722 is a complete low cost stereo audio dac, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo dac and output smoothing filters. a novel multi-bit sigma-delta dac design is used, utilising a 64x oversampling rate, to optimise signal-to- noise performance and increase clock jitter tolerance. the wm8722 also provides an analogue mixing function, which allows user-selectable control over mixing of an external analogue input signal (line level sources or microphone output) with the converted output signal. the device provides both line level and variable outputs. the wm8722 contains a high performance sine wave generator circuit, which can be used to generate low distortion sinusoidal waveforms of varying frequency and amplitude. the wm8722 uses a minimum of external components, with the internally generated mid- rail references used to provide dc bias of output signals requiring only a single external capacitor for decoupling purposes. the wm8722 is controlled through a software control interface. this allows control of variables such as gain levels through each path, tone frequency and duration, and audio data interface format. the software control interface may be operated using either a 3-wire (spi compatible) or 2-wire mpu interface. selection of interface format is achieved by monitoring the state of busy pin at power up. in 2-wire mode, the latch pin becomes an address select, allowing two wm8722 devices to be used on the same bus. operation using system clock of 256fs or 384fs is provided, selection between clock rates being automatically controlled. alternatively, the user can select the clock rate through the software interface. sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. tolerance of asynchronous word clock jitter is provided, the internal signal processing of the device re-synching to the external lrcin clock once the phase difference between left-right and system clocks exceeds half an lrcin period. during this re-synch period, the oversampling filters either miss an audio sample, or repeat the last sample value, so minimising the audible effects of this operation. the interface supports normal (right justified) and i 2 s (philips left justified, one bit delayed) interface formats, in both packed and unpacked forms. (packed has exactly the number of serial clocks corresponding to the number of data bits, per lrcin period). additionally the device automatically detects when it is connected to a 16 bit packed data source (32 serial clocks per lrcin) and switches automatically into 16 bit mode. 44.1khz de-emphasis is supported, with frequency scaling if other sample rates are used. the tone generator circuit uses a high quality sine weighted dac, and sophisticated noise shaping techniques to achieve high quality tones with low noise and spurious tone generation. using the nominal master tone clock (tclk) frequency of 27mhz, any frequency from 1hz to 32khz may be generated in 1hz increments. the duration of the tone burst may be programmed from 0.1second to 25.5 seconds. the next tone may be pre-programmed during a current tone burst, and is then loaded, in phase continuous manner at the end of the current tone so allowing continuous generation of varying frequency. the device is packaged in a small 5.3mm wide 20-pin ssop package. single 3v to 5v supplies may be used, the output amplitude scaling with absolute supply level. low supply voltage operation and low current consumption, the low pin count small package and the analogue mixing features, make the wm8722 attractive for many consumer audio applications, including vcd, cd, dvd-audio, set- top boxes and digital tv. separate analogue and digital supply pins are provided, allowing 3v operation of digital and 5v operation of analogue circuits. analogue mixer the analogue mixer circuits comprise signal paths to allow signal switching and gain adjust for each of the mixer line-in, dac output, and tone generator signals. additionally, mono signals can be created using the completely flexible switching arrangements, and 6db attenuation switching circuits. individual control bits are provided for each of the 5 switch inputs to each summing stage in the mixer, each signal path therefore being individually controllable. any combination of output signal is therefore permissible. fixed output level line outputs and volume adjusted variable output level outputs are provided.
wm8722 advanced information w w w w ai rev 2.1 june 2001 10 tone generator dac the tone generator comprises a digital frequency synthesiser, which is used to create a clock at 128x the required tone frequency, and a 128 step per cycle, sine weighted dac, which converts the clock into one of three tone types. an analogue programmable gain stage follows the dac, allowing gain adjustment of the tone amplitude. noise shaping techniques are used to create minimal spurious components in the frequency synthesiser. the wm8722 can generate three different tone types. the default setting is a sinusoidal tone. square waves are generated by setting the sqr bit. alternatively, a two-tone output that generates one cycle at the chosen frequency, followed by two cycles at twice that frequency can be selected by setting the f2f bit. this facility may be used in sine or square wave modes. the frequency of the resulting tone is controllable with 1hz resolution, over a range of 1hz to 32.767khz, based on a tclk frequency of 27mhz. alternative tone clock frequencies may be used if required. for example the dac sclk frequency may be used, but in these cases the frequency range and resolution will change by the ratio of the clock used, to the nominal 27mhz clock specified. the duration of the selected tone is programmed via the serial interface. once both the frequency and the duration have been set to non-zero values, the tone generation commences. once the tone generator has started running, the next tone frequency and duration may be programmed ready to start as soon as the current tone finishes. under this condition the tones are phase continuous, and a busy flag is set on the busy pin, which now becomes a cmos output, overdriving any pull-up or down resistor placed on the pin to select the interface format at power-up. after a tone frequency of duration has been written, it may be over written with a new value if desired. at the conclusion of a tone burst, the circuit ensures that at the end of the duration time of the last tone, the tone continues to the next zero crossing point to ensure dc offsets are not created. a control bit (tfin) is provided which allows selection of the method of completion of the burst: if set to 1, the burst completes at the next zero crossing. if left at 0, the burst completes a whole number of sinusoids, avoiding potential problems with dc levels changing across ac coupling capacitors. whilst tones are being generated, writing either new frequency or new duration, will cause the subsequent burst to be generated phase continuously with the current burst. if a duration value of 0 is written during a burst, the current burst will stop immediately (at the next zero cross or full cycle complete point as selected by tfin). if the current burst completes, and no new duration of frequency has been set, the tones stop and the duration value is reset to zero. the frequency setting is maintained in volatile memory. if a new duration is programmed, then the tone generator will re-start with the previously programmed frequency. if a new frequency is desired, the frequency is simply programmed before the duration, the tone commencing when the duration is written. system clock the system clock for the wm8722 must be either 256fs or 384fs where fs is the audio sampling frequency (lrcin), typically 32khz, 44.1khz, 48khz or 96khz. the system clock is used to operate the digital filters and the noise shaping circuits. wm8722 has system clock detection circuitry that automatically determines the relationship between the system clock frequency and the sampling rate (to within 8 system clocks). if greater than 8 clocks error, then the interface shuts down the dac and mutes the output. the system clock should be synchronised with lrcin, but wm8722 is tolerant of phase differences or jitter on this clock. severe distortion in the phase difference between lrcin and the system clock (for example caused by too many or too few system clocks received per lrcin period) will be detected, and cause the device to automatically re-synchronise. if the externally applied lrcin slips in phase by more than half the internal lrcin period, which is derived from the master clock, then the interface resynchronises. during re-synchronisation, the wm8722 will either repeat the previous sample or drop the next sample depending on the nature of the phase slip. this will ensure there is no discernible click at the analogue outputs during re-synchronisation.
wm8722 advanced information w w w w ai rev 2.1 june 2001 11 system clock frequency (mhz) sampling rate (lrcin) 256fs 384fs 32khz 8.192 12.288 44.1khz 11.2896 16.9340 48khz 12.288 18.432 96khz 24.576 36.864 table 1 system clock frequencies versus sampling rate audio data interface the serial data interface to wm8722 is fully compatible with both normal (msb first, right-justified) or i 2 s interfaces. data may be packed (number of serial blcks per lrcin period is exactly 2 times the number of data bits, i.e. normally 32 in 16 bit mode) or unpacked (more than 32 bclks per lrcin period. the wm8722 will automatically detect 16-bit packed data being sent to the device in normal mode, and accept the data in this input format accordingly. i 2 s mode description 0 normal format (msb-first, right justified) 1 i 2 s format (philips serial data protocol ) table 2 serial interface formats msb msb lsb lsb left channel right channel lrcin bckin din 1/fs 123 n n-1 n-2 123 n n-1 n-2 figure 5 normal data input timing msb msb lsb lsb left channel right channel lrcin bckin din 1/fs 123 n n-1 n-2 123 n n-1 n-2 figure 6 i 2 s data input timing
wm8722 advanced information w w w w ai rev 2.1 june 2001 12 modes of operation the software control interface may be operated using either a 3-wire (spi-compatible) or 2-wire mpu interface. selection of interface format is achieved by monitoring the state of busy pin at power up. in 3-wire mode, md is used for the program data, mc is used to clock in the program data and latch is used to latch in the program data. in 2-wire mode, md is used for serial data and mc is used for serial clock. in 2-wire mode, the latch pin allows the user to select one of two addresses. selection of serial control mode the serial control interface may be selected to operate in either 2 or 3-wire modes. this is achieved by setting the state of the busy pin at power-up with a weak, external pull-up or pull-down resistor (typically 10k). this pin is an input at power up, and its state selects the type of input format. the value input at power-up is sampled and stored internally. this allows the busy pin to be used as an output when tone generation has been enabled. this stored value is only reset when the device is powered off. busy pin (tone generation not enabled) interface format 0 3 wire 1 2 wire table 3 control interface mode selection 3-wire (spi compatible) serial control mode the wm8722 can be controlled using a 3-wire serial interface. md is used for the program data, mc is used to clock in the program data and latch is use to latch in the program data. the 3-wire interface protocol is shown in figure 7. please note that latch is edge sensitive not level sensitive. data is latched on a rising edge of latch. latch mc md b15 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 b4 b5 b0 figure 7 3-wire serial interface 2-wire serial control mode the wm8722 supports a 2-wire mpu serial interface. the device operates as a slave device only. the wm8722 has one of two slave addresses that are selected by setting the state of pin 5, (latch). md mc ack r addr ack data b15-8 stop start data b7-0 r/w ack figure 8 2-wire serial interface
wm8722 advanced information w w w w ai rev 2.1 june 2001 13 latch state address 1 1000001 (0x82) 0 1000000 (0x80) to control the wm8722 on the bus, the master must initiate a data transfer by establishing a start condition, defined by a high-to-low transition on md whilst mc remains high. this indicates that an address and data transfer will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/w bit). the transfer is msb first. the peripheral that recognises the transmitted address responds by pulling the data line low during the ninth clock pulse (acknowledge bit). all other devices withdraw from the bus and maintain an idle condition once the appropriate peripheral has been recognised. the idle condition is where the device monitors the md and mc lines waiting for a start condition and the correct transmitted address. the r/w bit determines the direction of data transfer. the wm8722 is a write only device and only responds to the r/w bit indicating a write. the wm8722 acts as a standard slave device on the bus. the data on the md is clocked in by mc. the first 6 bits (which must be 100000) are clocked into the wm8722 followed by a programmable address bit to select one of the two available addresses. the eighth bit of the address byte is the r/w bit. the wm8722 checks this bit and responds if it is a write. if the correct address is sent by the master, the wm8722 acknowledges the bus master (ack) and pulls the bus low. the next byte is the register address. each subsequent byte of data is separated by an acknowledge bit. a stop condition is defined when there is a low-to-high transition on md when mc is high. if a stop or start condition is detected out of sequence at any point in the data transfer, the device jumps to the idle condition. serial control operation control of the various modes of operation is software controled over the 2 or 3-wire serial interface. the following functions may be controlled via the serial control interface: function options software control default value input audio data format normal format i 2 s format normal format (0) input word length 16 20 24 16 bit (0) de-emphasis selection on off off (0) power off control enable disable enabled (0) analogue output mode l, r, mono, mute stereo (1001) mute on (muted) off (un-muted) off (0) input lrcin polarity lch/rch = hi/lo lch/rch = lo/hi lch/rch = hi/lo (0) master volume control lch, rch individually lch, rch both 0db (1111001) lch, rch individually (0)
wm8722 advanced information w w w w ai rev 2.1 june 2001 14 function options software control default value dac digital volume lch, rch individually lch, rch common 0db (111111) lch, rch individually (0) mixer volume control lch, rch individually lch, rch both 0db (10111) lch, rch individually (0) mixer output selection 5 switches for each of left and right, mix and volume paths, individually controlled, or both together, and with ?6db gain option for mono modes normal stereo (11100) mlmx left mux (11100) mlvmx left mux (11100) mrmx right mux (11100) mrvmx right mux m6db bits all 0 (gain 0db) tone amplitude 0 to ?46.5db in 1.5db steps plus mute 0db (11111) tone frequency 1 to 32767hz in 1hz steps (based on 27mhz tclk) 0 = disabled tone duration 0.1 to 25.5secs in 0.1sec steps 0 = disabled tone finish behaviour (tfin) 1 = full cycle sine wave 0 = next zero cross tone waveform sine or square wave 0 = sine 1 = square wave tone burst f or 2f 0 = f 1 = 2f table 4 control functions
wm8722 advanced information w w w w ai rev 2.1 june 2001 15 register map the wm8722 controls the device functions using 15 program registers, each of which is 16-bits long. these registers are all loaded via the serial control interface in either 2 or 3-wire mode. there are two type of control word; either tfreq, the tone frequency word, which is a single address bit followed by 15 data bits, or other types, which have 6 address bits, and 10 bits of data. other types have the lead address bit inverted compared to tfreq words, allowing use of a single write to load the required frequency. reg b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tfreq 1 f[14:0] r0 0 0 0 0 0 0 0 ldl dal [7:0] r1 0 0 0 0 0 0 1 ldr dar[7:0] r2 0 0 0 0 0 1 0 pl[3:0] iw1 iw0 pwd de mu r3 0 0 0 0 0 1 1 0 0 0 0 0 0 atc lrp i2s r4 0 0 0 0 1 0 0 both 0 0 mute mtriml[4:0] r5 0 0 0 0 1 0 1 both 0 0 mute mtrimr[4:0] r6 0 0 0 0 1 1 0 both zcen lvol[6:0] r7 0 0 0 0 1 1 1 both zcen rvol[6:0] r8 0 0 0 1 0 0 0 both 0 0 m6db0 lmxsel(4-0) r9 0 0 0 1 0 0 1 both 0 0 m6db1 rmxsel(4-0) r10 0 0 0 1 0 1 0 both 0 0 m6db2 lvmxsel(4-0) r11 0 0 0 1 0 1 1 both 0 0 m6db3 rvmxsel(4-0) r12 0 0 0 1 1 0 0 0 ttim[7:0] r13 0 0 0 1 1 0 1 f2f sqr tfin mute tvol[4:0] address data table 5 mapping of program registers
wm8722 advanced information w w w w ai rev 2.1 june 2001 16 register name reg address bit name description default value tfreq 1 f[14:0] tone frequency value 000 0000 0000 0000 register 0 000 0000 dal[7:0] ldl dac attenuation data for left channel attenuation data load control for left channel 111 1111 (0db) 0 register 1 000 0001 dar[7:0] ldr dac attenuation data for right channel attenuation data load control for right channel 111 1111 (0db) 0 register 2 000 0010 mu de pwd iw[1:0] pl[3:0] left and right dacs soft mute control de-emphasis control power off control input audio data bit length select output mode select 0 (not muted) 0 (de-emph off) 0 (power on) 00 (16 bit) 1001 (normal stereo) register 3 000 0011 i2s lrp atc audio data format select polarity of lrcin (pin 18) select attenuator control 0 ( normal format) 0 0 register 4 000 0100 mtriml[4:0] mute left mixer 1 attenuation data left mixer mute 10111 (0db) 0 (not mute) register 5 000 0101 mtrimr[4:0] mute right mixer 1 attenuation data right mixer mute 10111 (0db) 0 (not mute) register 6 000 0110 lvol[6:0] zcen both left volume 2 attenuation data zero cross enable update left + right channels 1111 001 (0db) 0 0 register 7 000 0111 rvol[6:0] zcen both right volume 2 attenuation data zero cross enable update right + left channels 1111 001 (0db) 0 0 register 8 000 1000 lmxsel m6db0 both left mixer output mux control m6db for left mix output update left + right channels 11100 (normal stereo) 0 (0db) 0 register 9 000 1001 rmxsel m6db1 both right mixer output mux control m6db for right mix output update right + left channels 11100 (normal stereo) 0 (0db) 0 register 10 000 1010 lvmxsel m6db2 both left variable output mux control m6db for left variable output update left + right channels 11100 (normal stereo) 0 (0db) 0 register 11 000 1011 rvmxsel m6db3 both right variable output mux control m6db for right variable output update right + left channels 11100 (normal stereo) 0 (0db) 0 register 12 000 1100 ttim[7:0] tone duration 000 0000 (no tone) register 13 000 1101 tvol[4:0] mute tfin sqr f2f tone amplitude tone mute tone burst finish on zero cross tone sine or square wave tone one cycle at f, two cycle at 2xf 11111 (max output) 0 (not muted) 0 (finish on full cycle) 0 (sine wave) 0 (normal f) table 6 internal register mapping register tfreq tone frequency this is the special register of 15 bit length with a single bit address, to allow values for the selected tone frequency from 1hz to 32767hz to be written in one word. writing 0 turns off the tone. f tone = (f tclk x t freq [15:0] )/27x10 6
wm8722 advanced information w w w w ai rev 2.1 june 2001 17 register 0/1 dac output attenuation a digital attenuator is provided to allow the levels of dac signals to be attenuated in the digital domain. register 0 (a[1:0] = 00) is used to control left channel attenuation. bits 0-7 (al[7:0]) are used to determine the attenuation level. the level of attenuation is given by: attenuation = [20.log10 (attenuation_data/255)] db bit 8 in register 0 (ldl) is used to control the loading of attenuation data in b[7:0]. when ldl is set to 0, attenuation data will be loaded into al[7:0], but it will not affect the attenuation level until ldl is set to 1. ldr in register 1 has the same function for right channel attenuation. attenuation levels are controlled by setting the register set al[7:0] (left channel) or ar[7:0] (right channel). attenuation levels are given in table 7. ax[7:0] attenuation level 00h - db (mute) 01h -48.16 db : : : : : : feh -0.034 db ffh 0db table 7 attenuation control levels register 1 (a[1:0] = 01)is used to control right channel attenuation in a similar manner. register 2 soft mute soft mute is controlled by setting bit 0 in register 2 (a[1:0]=10). a high level on bit 0 will cause the dac outputs to be muted, the effect of which is to ramp the signal down in the digital domain so that there is no discernible click. digital de-emphasis bit 1 (de) in register 2 (a[1:0]=10) is used to control digital de-emphasis. a low level on bit 1 disables de-emphasis whilst a high level enables de-emphasis. power off control bit 2 (pwd) in register 2 is used for operation control. with pwd = low (default) the device functions normally. with pwd = high the device is disabled and the outputs are held at midrail. current consumption of the digital section is minimised, but analogue bias sections remain active in order to preserve dc levels. input word resolution bits 3 and 4 of register 2 (iw[1:0]) are used to determine the input word resolution. the wm8722 supports 16-bit, 18-bit, 20-bit and 24-bit word formats. bit 4 (iw1) bit 3 (iw0) input resolution 0 0 16-bit data word 0 1 20-bit data word 1 0 24-bit data word 1 1 18-bit data word table 8 input data resolution
wm8722 advanced information w w w w ai rev 2.1 june 2001 18 dac output control bits 5, 6, 7 and 8 (pl[3:0]) of register 2 are used to control the output format. pl0 pl1 pl2 pl3 left output right output note 0 0 0 0 mute mute mute both channels 0 0 0 1 mute r 0 0 1 0 mute l 0 0 1 1 mute (l + r)/2 0 1 0 0 r mute 0 1 0 1 r r 0 1 1 0 r l reverse channels 0 1 1 1 r (l + r)/2 1 0 0 0 l mute 1 0 0 1 l r stereo mode 1 0 1 0 l l 1 0 1 1 l (l + r)/2 1 1 0 0 (l + r)/2 mute 1 1 0 1 (l + r)/2 r 1 1 1 0 (l + r)/2 l 1 1 1 1 (l + r)/2 (l + r)/2 mono mode table 9 programmable output format register 3 audio data input format wm8722 allows maximum flexibility over the control of the audio data interface, allowing selection of format type, word length, and sample rates. digital audio serial protocol a low on bit 0 sets the format to normal (msb-first, right justified format), whilst a high sets the format to i 2 s (philips serial data protocol). audio interface clocks bit 1 (lrp) of register 3 is used to control the polarity of lrcin (sample rate clock). when bit 1 is low, left channel data is assumed when lrcin is in a high phase and right channel data is assumed when lrcin is in a low phase. when bit 1 is high, the polarity assumption is reversed. attenuator control bit 2 in register 3 (a1[1:0] = 11) is used to control the attenuator (atc). when atc is high, the attenuation data loaded in program register 0 is used for both the left and the right channels. when atc is low, the attenuation data for each register is applied separately to left and right channels. register 4/5 analogue mixer trim bits 0-4 of register 4, mtriml[0:4], set the gain level of the first stage of analogue mixing on the left channel. the 5-bit register selects 1.5 db increments of the mixinl signal, over a range of +12db to ?34.5db. a 6 th bit, mute, controls muting of the signal when set high. similarly, bits 0-4 of register 5, mtrimr[0:4], set the attenuation level of the first stage of analogue mixing on the right channel. the 5-bit register allows 1.5 db increments of the mixinr signal, over a range of +12db to ?34.5db. a 6 th bit, mute, controls muting of the signal when set high.
wm8722 advanced information w w w w ai rev 2.1 june 2001 19 both in register 4 and 5, a further bit both is available: when a write is made to either register 4 or 5 and both is set high, then the same value written to the register will also be written into the other register. this allows both left and right channel gains to be updated simultaneously, halving the number of serial writes required, (simplifying gain ramping, for example) provided that the same gain is needed for both channels. register 6/7 volume control bits 0-6 of register 6, lvol[6:0], control gain applied to the variable level output varoutl. this 6- bit register controls 1.0 db increments of the volume, over a range of +6 db to ?73 db. similarly bits 0-6 of register 7, rvol[6:0], control the gain applied to the variable level output varoutr. value 1111111 sets maximum, i.e. 6db gain. code 48 sets minimum gain. values less than code 48 apply mute to the gain stage. (i.e. set volume to 000 0000 to achieve mute) zcen a zero cross detect circuit is provided, so that volume control values are only updated when the input signal to the gain stage is close to the analogue ground level, minimising clicks and zipper noise as the gain values are changed. this circuit has no time out so if dc levels are being applied to the gain stage input, then the gain will not be updated. this zero cross function is enabled when the zcen bit is set high during a volume register write. if there is concern that a dc level may have blocked a volume change (one made with zcen set high), then a subsequent volume write of the same value, but with the zcen bit set low will force a volume update regardless of the dc level. both in register 6 and 7, a further bit both is available. when a write is made to either register 6 or 7 and both is set high, then the same value written to the register will also be written into the other register. this allows both left and right channel gains to be updated simultaneously, halving the number of serial writes required, provided that the same gain is needed for both channels. register 8, 9, 10, 11 analogue mixer output selection the wm8722 allows software controllable selection of signal outputs. the wm8722 allows 2 outputs per channel, with one output at line level, and another output at variable level, according to the lvol[6:0] and rvol[6:0] attenuation register settings. in addition, the user may select whether the left or the right signal, converted in the dac, is mixed with the corresponding mixer input or not. this switching scheme is detailed in figure 9, with 10 different select signals per channel, 5 each for each mux: each mux therefore has 5 input signals; dacl, dacr, mixl, mixr and tone. this allows completely flexible selection of signal paths, both mono and stereo outputs, on any output. mux control bits mxsel(4:0) signal selected when high is set 0 dac sum enable 1 mixin sum enable 2 tone in sum enable 3 opposite channel dac sum enable 4 opposite channel mixin sum enable table 10 mux(4:0) mux control switches if mono outputs are selected, the gain through the summer amplifiers may be reduced by 6db if required by setting the appropriate m6db bits. similarly left and right channels may be completely swapped.
wm8722 advanced information w w w w ai rev 2.1 june 2001 20 mxinr mxinl lineoutl varoutl varoutr lineoutr + + + + 0/-6db 0/-6db 0/-6db l mix switches (0-9) 0/-6db r mix switches (0-9) tone dac left dac right dac figure 9 output mixer configuration m6db in each of the 4 mux control registers there is an m6db bit relevant to that channel. setting m6db high reduces the relevant output signal by 6db. both when a write to any mxsel register is made with the both bit set high, then the complementary channel mxsel register for the other channel is updated with the same value. for example, if rvmxsel is updated and both is set, then lvmxsel is updated with the same value, but the rmxsel and lmxsel registers (the non variable output path muxes) are not updated. register 12 tone duration bits 0-7 of register 12 sets the duration of the tone burst. writing to the register with a non-zero value starts the tone burst. wring zero to this register stops the tone. t = (2.7x10 6 x ttim[7:0])/ f tclk register 13 tone generator gain control bits 0-4 of register 13 tvol[0:4] set the gain level of the tones summed into the analogue outputs. bit 5 of this word controls muting of the tones. note both mute must be off (0) and the tone input to the relevant mixer summing path must be selected (1). the gain defaults to 0db (11111) but may be attenuated in 1.5db steps down to ?46.5db. tone generator waveform control tfin a control bit (tfin) is provided which allows selection of the method of completion of the burst. if set to 1, the burst completes at the next zero crossing. if left at 0, the burst completes a whole number of sinusoids, avoiding potential problems with dc levels changing across ac coupling capacitors. at the conclusion of a tone burst, the circuit ensures that at the end of the duration time of the last tone, the tone continues to the next zero crossing point to ensure dc offsets are not created.
wm8722 advanced information w w w w ai rev 2.1 june 2001 21 sqr the wm8722 can generate three different tone types. the default setting is a sinusoidal tone. square waves are generated by setting the sqr bit. f2f a two-tone output that generates one cycle at the chosen frequency, followed by two cycles at twice that frequency can be selected by setting the f2f bit. this facility may be used in sine or square wave modes. system diagram storage (hdd) video dac digital decoder media front end home connectivity system clocks wm8722 audio dac amplifier video out tone generator output mono audio output (optional) l r l r variable level audio output (tv) line level audio output (vcr) headphone out mic or analogue input figure 10 digital set top box application the wm8722 is a complete audio sub-system designed for digital set top box applications. a typical application might require audio outputs to be routed to a vcr and television. the wm8722 allows the user to control the output audio level being sent to the television whilst maintaining a constant volume level to the vcr. the on-chip tone generator can be programmed to provide a audible warning signal from the set top box to the television outputs without appearing on the line level outputs. the wm8722 can also directly generate a mono signal for uhf outputs. the wm8722 contains a stereo analogue input. this signal can be routed or mixed together onto the line and variable outputs. it can be used to control the volume level of an audio output from another audio source such as a games machine or additional set top box. alternatively, it could be used to provide a karaoke input from a digital effects processor.
wm8722 advanced information w w w w ai rev 2.1 june 2001 22 recommended external components 2 dvdd dgnd mc agnd avdd cap c 12 c 11 agnd 16 6 spi or 2-wire interface wm8722 notes: 1. agnd and dgnd should be connected as close to the wm8722 as 2. c 2 , c 3 , c 9 , c 10 and c 11 should be positioned as close to the wm8722 as 3. capacitor types should be carefully chosen. capacitors with very low recommended for optimum c 3 c 4 c 2 dvdd c 1 3 md 4 latch varoutr 12 c 5 varoutl c 6 ac-coupled variable outputs to external lpf 9 avdd 1 tclk 17 din 18 lrcin 20 scki audio serial data i/f dgnd agnd lineoutr 13 c 7 lineoutl c 8 ac-coupled line level outputs to external lpf 8 5 busy 19 bckin 11 10 + + + + + 15 + + 7 mxinr 14 mxinl c 9 c 10 2-wire interface spi interface dvdd dgnd r1 figure 11 external components diagram recommended external components values component reference suggested value description c1 and c4 10 f de-coupling for dvdd and avdd. c2 and c3 0.1 f de-coupling for dvdd and avdd. c5, c6, c7 and c8 10 f output ac coupling caps to remove midrail dc level from outputs. c11 0.1 f c12 10 f reference de-coupling capacitors for cap pin. r1 10k ? c9,c10 1 f ac coupling capacitors for setting dc inputs level of analogue table 11. external components description
wm8722 advanced information w w w w ai rev 2.1 june 2001 23 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.a ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 ----- 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 e 1 5.00 5.30 5.60 l 0.55 0.75 0.95 0 o 4 o 8 o ref: jedec.95, mo-150 c l gauge plane 0.25 a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e
wm8722 advanced information w w w w ai rev 2.1 june 2001 24 important notice wolfson microelectronics ltd (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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